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ISSN: 2641-3086
Trends in Computer Science and Information Technology
Review Article       Open Access      Peer-Reviewed

A study of converter configurations for vehicular applications

Ankur Kumar Gupta1, Uliya Mitra2* and Hemant Kumar Verma3

1Department of Electrical Engineering, G.H. Raisoni College of Engineering, Nagpur, India
1,2Department of Electrical Engineering, Maulana Azad National Institute of Technology, Bhopal, India
3Department of Electrical & Electronics Engineering, Bhilai Institute of Technology, Raipur, India
*Corresponding author: Uliya Mitra, Department of Electrical Engineering, Maulana Azad National Institute of Technology, Bhopal, India, E-mail: uliya0289.mitra@gmail.com
Received: 30 January, 2024 | Accepted: 19 February, 2024 | Published: 20 February, 2024
Keywords: DC-DC converters; Wide voltage gain; Non-isolated converters; Isolated converters; Energy conversion

Cite this as

Gupta AK, Mitra U, Verma HK (2024) A study of converter configurations for vehicular applications. Trends Comput Sci Inf Technol 9(1): 010-022. DOI: 10.17352/tcsit.000075

Copyright License

© 2024 Gupta AK, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.

Renewable energy sources like hydro, wind, geothermal and solar along with fuel cells are nowadays solutions to the global energy crisis, environmental issues, and fossil fuel exploitation. The nature of the output of these renewable sources is D.C. The role of DC-DC converters in the integration of energy sources with microgrids is vital. These converters find their major applications in power generation, energy systems, vehicular applications, portable electronic devices, aerospace, etc. These converters help to boost the voltage and improve the reliability, stability, efficiency, and performance of the system. This study gives a brief overview of three DC-DC converters of non-isolated topology. They are: Clamped H-type boost DC-DC converter, Multi-Port Dual-Active-Bridge DC-DC Converter, and Four-Phase Interleaved Four-Switch Buck-Boost Converter. This study will make researchers learn and make their concept clear about the operation, performance, and usage of these converters.

Introduction

The rising concern of pollution and energy shortage has led human society to shift towards clean and sustainable energy sources. Integration of renewable energy sources like solar, wind, hydro, etc. into microgrids has opened ways for mitigating growing energy demand [1,2]. The output of these sources are D.C supply. Electric Vehicles (EV) and Fuel Cell Electric Vehicles (FCEV) are substitutes for conventional vehicles. These vehicles use electric motors in place of IC engines [3,4]. The power electronic converters act as the intermediaries between power generation and load. They have replaced conventional voltage divider circuits, power conversion circuits, and rheostats which have low efficiency and low output voltage [5,6]. The DC-DC converters were first introduced in the year 1920. They have a wide area of application. Converters stabilize the output voltage of the system during intermittent conditions. The quality of power obtained from renewable energy systems depends heavily on the control technique and stable operation of the power converter [7-9]. Boost converters were the first converters used; all converters are derived from this. Boost converters are more widely and popularly used when it comes to renewable energy applications as they are simple in design [10]. Theoretically, the voltage gain in the case of a boost converter can go to infinity for unity as the duty cycle. But, with an increase in duty cycle, there are certain issues like shorter turn-off period of a switch, increased conduction losses, current ripples, turn-off current, and high voltage stress which makes the cost of high voltage stress switch more [11].

To improve the reliability of the system and to achieve a constant output voltage at the load side, a wide voltage gain DC-DC converter is used to connect with a high-voltage DC bus [12,13]. The DC-DC converters used for this purpose should have some specific features like high efficiency, high reliability, and small size [14]. The selection of a proper DC-DC converter for the desired application is a very crucial step as it affects the system’s output and operating performance largely. In the case of FCEVs, the converter used must have a continuous input current and low current ripple [15]. The DC-DC converters in the literature are classified based on isolated and non-isolated topologies for obtaining wide voltage gain. An isolated DC-DC converter has a high-frequency transformer located between the input and output side to provide galvanic isolation [16] to protect sensitive loads by enhancing safety and also transmitting the input power to the output side. The output in these converters has a high immunity to noise interference. They are more suitable for applications where a high voltage gain ratio is required due to a magnetic transformer. This makes the converter bulky and complex. In the case of two-stage power transformation, the two stages are DC-AC-DC [17]. The non-isolated DC-DC converters are cost-effective, simple in design, and do not have galvanic isolation. Researches are carried out on non-isolated converters for improved switching, enhanced efficiency, fault-tolerant operation, control and switching strategies, and renewable energy applications [18-20]. The non-isolated type of DC-DC converters due to their high efficiency and low cost are used in FCEVs. Figure 1 shows different types of converters.

The non-isolated converters of high voltage gain mainly focus on multistage techniques, switched capacitors, voltage multipliers, switched inductors, and coupled inductors [21,22]. It is easy to achieve high voltage gain in a coupled inductor converter but a large current ripple is seen in the case of a single-stage single-phase-coupled inductor converter which reduces the life span of FCs in FCEV [23]. A switched inductor converter attains high voltage gain but it exerts a high voltage stress on diodes [24]. A boost-type DC-DC converter can provide a wide voltage range when used with a switched capacitor structure [25]. A three-level DC-DC boost converter having low input current ripple and limited voltage gain for interfacing fuel cell stack is presented in [26]. A high-frequency Pulse Width Modulation (PWM) voltage is applied between the grounds of the input and output port which causes Electromagnetic Interference (EMI) problems and maintenance issues. A common ground structure to increase the reliability of the converter is presented in [27]. A converter having a wide input voltage range, lower voltage gain, low input current ripple, and non-common ground topology is presented in [28]. A larger duty cycle enhances the voltage gain but it also increases the conduction loss in power switches. A switched capacitor-based double switch boost converter with a non-common ground topology of duty cycle in the range 0-0.5 to reduce conduction loss of power switch is proposed in [29]. This study gives an overview of three such converters namely a Clamped H-type boost DC-DC converter With a Wide Voltage-Gain Range, a Multi-Port Dual-Active-Bridge DC-DC Converter, and a Four-Phase Interleaved Four-Switch Buck-Boost Converter. The converters are explained in sections II, III, and IV respectively. The study is concluded in section V.

Clamped H-type boost DC-DC converter

The clamped H-type boost DC-DC converter is interfaced with the FC stack in FCEVs where it works as a step-up device. The output voltage of FC stacks is DC in nature and of low value which cannot be used directly and is thus boosted and regulated using a step-up stage. This converter has various advantages such as a wide input voltage range, high voltage gain, minimum conduction losses, reduced input current ripple, and voltage stress on capacitors and power semiconductors. This increases the efficiency and reliability of the converter making it capable of use in FCEV. The authors in [30] used this converter along with a switched capacitor structure. The capacitor-clamped H-type structure consists of two switches S1, S2 along with Q1, Q2, diodes D1, and D2, capacitor C1, and inductor L. The structure of the switched capacitor consists of diodes D3, D4, and D5 and capacitors C2, C3, and C4. The advantages of the inclusion of a switched capacitor structure are a reduction in voltage stress from semiconductors and capacitors and high voltage gain. A Switched-capacitor-based DC-DC converter was proposed in [31] with one capacitor and one diode less than this converter and a higher voltage gain. A non-common ground of input-output, large input current ripple, and one diode with high voltage stress were some of its disadvantages. The analysis of the clamped converter is done during the continuous conduction of the input current. The duty cycle of Q1 is d1 and Q2 is d2 where d1=d2=d with 1800 phase difference between the two gates signals [30]. The operating condition of Q1 and Q2 decides the number of switching states. A total of four switching states for operation are there. They are 00, 01, 10, and 11. The value ‘0’ represents the OFF state and ‘1’ represents the ON state of the power switches. The switching state 11 is achieved only when the value of duty cycle d is higher than 0.5. During the range of the duty cycle between 0.5-1, the switching states are 01, 10 & 11 which means at least one switch among Q1 and Q2 has to be in the ON state, leading to continuous charging of the inductor. Due to this, the range of the converter’s duty cycle lies between 0 to 0.5.

The sequence of three switching states of the converter during each switching period is 10-00-01-00. During S1S2 =10 as depicted in Figure 2(a), the switch Q1 is ON and Q2 is in OFF condition. The polarization of diodes D1, and D4 is inverse whereas for diodes D2, D3 & D5 it is direct. The charging of inductor L is accomplished through a rising current iin linear in nature. A parallel connection could be observed between capacitors C1 and C4 as well as between C2 and C3. Further, a series of connections of these elements is done to supply power to the load. S1S2 = 00 indicates the OFF state of switches Q1 and Q2 as shown in Figure 2(b). In this case, a direct polarization of diodes D1, D2, D3, and D5 is observed whereas inverse polarization of diode D4 is done. A linear decrement in the inductor current could be observed. The energy of inductor L is transferred to C1 and C4. Inductors L and C2 not only charge the capacitor C3 but also supply the load. The switch Q1 is in OFF condition whereas Q2 is in ON condition during S1S2=01. This is shown in Figure 2(c). Here, D1 and D4 are directly polarized whereas the diodes D2, D3, and D5 have inverse polarization. The inductor L gets charged through the current iin that has a linear incremental nature. A parasitic resistance limits the current of diode D4 of the converter. Capacitor C4 charges C2 whereas C3 supplies the load. Figure 2(d) represents an equivalent circuit of the converter.

This converter offers a wide input voltage range along with high voltage gain. The verification of these converters is possible for all ideal components. The values of inductances and capacitances are considered to be large enough with constant voltages appearing across the capacitors. The diodes D1 and D5 are forward-biased. The voltages across C1 and C4 are equal as they are connected in parallel same is the case with capacitance C2 and C3. The expression of the voltage gain of this converter while operating in continuous current mode can be deduced using volt second balance of the inductor:

{ 2 V in d+( V in V 1 )( 12d )=0 V 1 = V 2 = V 3 = V 4 V 0 = V 3 + V 4 }        (1) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabmqaaaGcbaqcLbsapeGaaGOmaiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadMgacaWGUbaal8aabeaajugib8qacaWGKbGaey4kaSscfa4aaeWaaOWdaeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaWGPbGaamOBaaWcpaqabaqcLbsapeGaeyOeI0IaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGymaaWcpaqabaaak8qacaGLOaGaayzkaaqcfa4aaeWaaOWdaeaajugib8qacaaIXaGaeyOeI0IaaGOmaiaadsgaaOGaayjkaiaawMcaaKqzGeGaeyypa0JaaGimaaGcpaqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaigdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaikdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaiodaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaisdaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGimaaWcpaqabaqcLbsapeGaeyypa0JaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maaWcpaqabaqcLbsapeGaey4kaSIaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGinaaWcpaqabaaaaaGcpeGaay5Eaiaaw2haaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabgdacaqGPaaaaa@7CC8@

Where, Vin represents input voltage, V0 represents output voltage, V1, V2, V3, V4 represents the voltage across the capacitors namely C1, C2, C3 and C4. Eqn. (1) could be rewritten as:

V 0 = 2 12d V in       (2) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaicdaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaaGOmaaGcpaqaaKqzGeWdbiaaigdacqGHsislcaaIYaGaamizaaaacaWGwbqcfa4damaaBaaaleaajugib8qacaWGPbGaaeOBaaWcpaqabaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabkdacaqGPaaaaa@4C1C@

V 1 = V 2 = V 3 = V 4 = 1 12d V in        (3) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaigdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaikdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaiodaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaisdaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaaGymaaGcpaqaaKqzGeWdbiaaigdacqGHsislcaaIYaGaamizaaaacaWGwbqcfa4damaaBaaaleaajugib8qacaWGPbGaaeOBaaWcpaqabaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqGZaGaaeykaaaa@5AFD@

On the basis of eqn. (2) and eqn. (3), the voltage gain can be determined by:

M= 2 12d        (4) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaad2eacqGH9aqpjuaGdaWcaaGcpaqaaKqzGeWdbiaaikdaaOWdaeaajugib8qacaaIXaGaeyOeI0IaaGOmaiaadsgaaaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqG0aGaaeykaaaa@45A1@

Where d is the duty factor of range 0

t on M2 M ×T       (5) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadshajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gacaWGUbaal8aabeaajuaGpeWaaSaaaOWdaeaajugib8qacaWGnbGaeyOeI0IaaGOmaaGcpaqaaKqzGeWdbiaad2eaaaGaey41aqRaamivaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeynaiaabMcaaaa@49E2@

The value of the average inductor current IL can be found out by:

I L = 2 12d × V o R       (6) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadMeajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaaGOmaaGcpaqaaKqzGeWdbiaaigdacqGHsislcaaIYaGaamizaaaacqGHxdaTjuaGdaWcaaGcpaqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcbaqcLbsapeGaamOuaaaajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeOnaiaabMcaaaa@502C@

Here, R represents the load resistor. During S1S2=10, a linear increment of inductor current occurs which can be given by

i L = d× V in Lf       (7) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiabloBjwjaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaamizaiabgEna0kaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadMgacaqGUbaal8aabeaaaOqaaKqzGeWdbiaadYeacaWGMbaaaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqG3aGaaeykaaaa@4EAE@

The inductor ripple current is denoted by iL and switching frequency is denoted by f. The value of the current ripple ratio r for an inductor can be determined by using eqn. (6) and eqn. (7):

r= i L I L d ( 12d ) 2 ×R 4Lf       (8) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadkhacqGH9aqpjuaGdaWcaaGcpaqaaKqzGeWdbiabloBjwjaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaaGcbaqcLbsapeGaamysaKqba+aadaWgaaWcbaqcLbsapeGaamitaaWcpaqabaaaaKqba+qadaWcaaGcpaqaaKqzGeWdbiaadsgajuaGdaqadaGcpaqaaKqzGeWdbiaaigdacqGHsislcaaIYaGaamizaaGccaGLOaGaayzkaaqcfa4damaaCaaaleqabaqcLbsapeGaaGOmaaaacqGHxdaTcaWGsbaak8aabaqcLbsapeGaaGinaiaadYeacaWGMbaaaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqG4aGaaeykaaaa@59EA@

In real time, the value of M is kept between 5 and 16. For M greater than 5, there is a decrement in the ripple ratio of the input current of this converter leading to a continuous waveform of input current. The value of r is 28.5% when the voltage gain reaches 16.

Since, D1 and C1, Q2 and C1, and D4 and C2 are in a parallel state when Q2, D1, and D4 are in an OFF state whereas Q1, D2, and D3 are in ON states, the voltage across the parallel-connected power semiconductors will be equal. The voltage across these components is shown in eqn. (9)

{ V Q2 = V D1 = V C1 = 1 2 V o V D3 = V D4 = V C2 = 1 2 V o V Q1 = V D2 = V C1 = 1 2 V o V D5 = V D3 = 1 2 V o }       (9) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabqqaaaaakeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaWGrbGaaGOmaaWcpaqabaqcLbsapeGaeyypa0JaamOvaKqba+aadaWgaaWcbaqcLbsapeGaamiraiaaigdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadoeacaaIXaaal8aabeaajugib8qacqGH9aqpjuaGdaWcaaGcpaqaaKqzGeWdbiaaigdaaOWdaeaajugib8qacaaIYaaaaiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaamiraiaaiodaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadseacaaI0aaal8aabeaajugib8qacqGH9aqpcaWGwbqcfa4damaaBaaaleaajugib8qacaWGdbGaaGOmaaWcpaqabaqcLbsapeGaeyypa0tcfa4aaSaaaOWdaeaajugib8qacaaIXaaak8aabaqcLbsapeGaaGOmaaaacaWGwbqcfa4damaaBaaaleaajugib8qacaWGVbaal8aabeaaaOqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadgfacaaIXaaal8aabeaajugib8qacqGH9aqpcaWGwbqcfa4damaaBaaaleaajugib8qacaWGebGaaGOmaaWcpaqabaqcLbsapeGaeyypa0JaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4qaiaaigdaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaaGymaaGcpaqaaKqzGeWdbiaaikdaaaGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4BaaWcpaqabaaakeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaWGebGaaGynaaWcpaqabaqcLbsapeGaeyypa0JaamOvaKqba+aadaWgaaWcbaqcLbsapeGaamiraiaaiodaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaaGymaaGcpaqaaKqzGeWdbiaaikdaaaGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4BaaWcpaqabaaaaaGcpeGaay5Eaiaaw2haaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeyoaiaabMcaaaa@9B9D@

This shows that in this converter the voltage stress across all capacitors and power semiconductors is half of the output voltage. This converter also possesses a frequency doubling characteristic which leads to a reduction of the volume of the capacitor and inductor used here. The major limitation of this converter is its usage of five diodes which increases the reverse recovery losses and conduction losses which further decreases the efficiency of this converter. However, the power switches of this converter have small conduction losses. The waveform of this converter is shown in Figure 3.

Current-fed hybrid dual active bridge DC-DC converter

The converter consists of four power MOSFETS S1, S2, S3, and S4 at the input side operating as a dual boost half-bridge converter along with two inductors L1 and L2. The output side consists of an auxiliary half-bridge and a full bridge [32]. A similar current-fed DC/DC converter is proposed in [33] based on the FC model and load disturbance conditions. The auxiliary half bridge is constructed using S9 and S10 MOSFETS whereas the full bridge is constructed of four MOSFETS namely S5, S6, S7, and S8. A high-frequency transformer with a turn ratio of 1: n connects the two sides. The transformer’s leakage inductance is represented by L. Figure 4 represents this converter. The converter has a voltage conversion ratio that is given by:

M= V 0 2n V in      (10) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaad2eacqGH9aqpjuaGdaWcaaGcpaqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaicdaaSWdaeqaaaGcbaqcLbsapeGaaGOmaiaad6gacaWGwbqcfa4damaaBaaaleaajugib8qacaWGPbGaamOBaaWcpaqabaaaaKqba+qacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqGXaGaaeimaiaabMcaaaa@4A07@

At the input side, the switches S1 and S2, S3 and S4 are operated complimentarily with a fixed duty cycle of 50%. The switches S2 and S4 are separated by a phase shift of Ts/2. The switching period is denoted by Ts. On the output side, switches S5 and S6, S7 and S9, and S8 and S10 are also complement to each other. S5 and S6 have a fixed duty cycle of 50% whereas the gating signal of power switch S5 lags behind S1 by a phase shift ratio of φ. The power switches S7 and S8 are turned on along with S5 and S6. The Zero-Voltage Switching (ZVS) for a wide operating range can be obtained for all switches for an appropriate duty cycle. iL denotes the current flowing through the leakage inductor. The voltage across points 1 & 2 is represented by V12 whereas V34 represents the voltage across points 3 & 4.

The operation of the entire switching period of this converter could be separated into 12 stages but due to symmetry in the operating mode, the half-switching cycle will be discussed since the other half is similar to it. The configurations of the converter at different durations of the switching periods from t1-t7 are shown in Figure 4(a-f) respectively. Before t1, the power switches S1, S3, S7, S9, S10 are on and iL decreases linearly. At the instant t1, S1, and S3 are turned off. This makes the junction capacitors attached to the switches at the input side resonate with L, L1, and L2. The difference between the currents iL1 and iL charges the capacitor of S2 and discharges the capacitor of S1 until the voltage across the drain to the source of S1 reaches zero. After that, the diode of S1 will start conduction after the gating signal of S1. Similarly, the sum of iL and IL2 will charge the capacitor of S3 and discharge the capacitor of S4 until ZVS is obtained. At instant t2, S1, and S4 are turned ON. The ZVS can be obtained if L, L1, and L2 are properly designed. After the completion of the resonance period, V12 is equal to Vc and V34 is equal to –V0/2 which results in a linear increment of IL. At this time, the voltage across both S7 and S8 is V0/2. This can be represented by the following equation:

{ V 12 = V c V 34 = V o 2 i L ( t )= i L ( t 2 ) V 12 V 34 /n L ( t t 2 ) }       (11) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabmqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGymaiaaikdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maiaaisdaaSWdaeqaaKqzGeWdbiabg2da9iabgkHiTKqbaoaaliaak8aabaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4BaaWcpaqabaaakeaajugib8qacaaIYaaaaaGcpaqaaKqzGeWdbiaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshaaOGaayjkaiaawMcaaKqzGeGaeyypa0JaamyAaKqba+aadaWgaaWcbaqcLbsapeGaamitaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaKqba+aadaWgaaWcbaqcLbsapeGaaGOmaaWcpaqabaaak8qacaGLOaGaayzkaaqcfa4aaSaaaOWdaeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaaIXaGaaGOmaaWcpaqabaqcLbsapeGaeyOeI0IaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maiaaisdaaSWdaeqaaKqzGeWdbiaac+cacaWGUbaak8aabaqcLbsapeGaamitaaaajuaGdaqadaGcpaqaaKqzGeWdbiaadshacqGHsislcaWG0bqcfa4damaaBaaaleaajugib8qacaaIYaaal8aabeaaaOWdbiaawIcacaGLPaaaaaaacaGL7bGaayzFaaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqGXaGaaeymaiaabMcaaaa@8115@

S6 and S10 are turned off at t3. The junction capacitors of S6, S7, and S10 will get charged whereas junction capacitors of S5 and S8 will discharge due to secondary current i2 of the transformer till voltage across S5 and S8 reaches zero. The voltage across S6 and S7 increases to Vo whereas across S10 the voltage increases to Vo/2. This results in the conduction of body diodes of S5 and S8 until their gate signals arrive. At time instant t4, the power switches S5 and S8 are turned on with the ability of ZVS. The value of Vc is less than Vo/n, which will result in a linear decrease of current IL as per the relationship given in eqn. (12). At this condition, there will be no flow of secondary current i2 through the bidirectional switch constructed by S9 and S10. At t5, the switch S8 is turned off. The junction capacitors of S8 will be charged whereas that of S7 and S10 will be discharged due to i2 till the VDS voltage of S8 gets incremented and reaches Vo/2 whereas that of S7 falls to Vo/2 and S10 falls to zero. Although S9 is still on but then also the conduction by the body diode of S10 initiates. Finally, at t6 when iL is negative the S10 gets turned on with ZVS after which a linear increment could be observed in the current iL as per the relation mentioned in eqn. (13).

{ V 12 = V c V 34 = V o i L ( t )= i L ( t 4 ) V 12 V 34 /n L ( t t 4 ) }       (12) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabmqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGymaiaaikdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maiaaisdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcbaqcLbsapeGaamyAaKqba+aadaWgaaWcbaqcLbsapeGaamitaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaaGccaGLOaGaayzkaaqcLbsacqGH9aqpcaWGPbqcfa4damaaBaaaleaajugib8qacaWGmbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacaWG0bqcfa4damaaBaaaleaajugib8qacaaI0aaal8aabeaaaOWdbiaawIcacaGLPaaajuaGdaWcaaGcpaqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaaigdacaaIYaaal8aabeaajugib8qacqGHsislcaWGwbqcfa4damaaBaaaleaajugib8qacaaIZaGaaGinaaWcpaqabaqcLbsapeGaai4laiaad6gaaOWdaeaajugib8qacaWGmbaaaKqbaoaabmaak8aabaqcLbsapeGaamiDaiabgkHiTiaadshajuaGpaWaaSbaaSqaaKqzGeWdbiaaisdaaSWdaeqaaaGcpeGaayjkaiaawMcaaaaaaiaawUhacaGL9baajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabgdacaqGYaGaaeykaaaa@7D61@

{ V 12 = V c V 34 = V o 2 i L ( t )= i L ( t 6 ) V 12 V 34 /n L ( t t 6 ) }      (13) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabmqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaGymaiaaikdaaSWdaeqaaKqzGeWdbiabg2da9iaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maiaaisdaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaaliaak8aabaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4BaaWcpaqabaaakeaajugib8qacaaIYaaaaaGcpaqaaKqzGeWdbiaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshaaOGaayjkaiaawMcaaKqzGeGaeyypa0JaamyAaKqba+aadaWgaaWcbaqcLbsapeGaamitaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaKqba+aadaWgaaWcbaqcLbsapeGaaGOnaaWcpaqabaaak8qacaGLOaGaayzkaaqcfa4aaSaaaOWdaeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaaIXaGaaGOmaaWcpaqabaqcLbsapeGaeyOeI0IaamOvaKqba+aadaWgaaWcbaqcLbsapeGaaG4maiaaisdaaSWdaeqaaKqzGeWdbiaac+cacaWGUbaak8aabaqcLbsapeGaamitaaaajuaGdaqadaGcpaqaaKqzGeWdbiaadshacqGHsislcaWG0bqcfa4damaaBaaaleaajugib8qacaaI2aaal8aabeaaaOWdbiaawIcacaGLPaaaaaaacaGL7bGaayzFaaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabgdacaqGZaGaaeykaaaa@7F8F@

The duty cycle d at the output side and phase shift ratio φ control the transferred power Po by the converter [32]. Different waveforms of iL for fixed input power and voltage are achieved by varying the possible combinations of φ & d which further leads to different ZVS conditions. The waveforms showing the operation of this converter theoretically are represented in Figure 5. The switches are turned on during t1-t5. The value of current iL flowing through leakage inductance L at these moments can determine the Zero Voltage Switching value. A piecewise relation exists between P0 and φ. For Vin>30V, a non-monotonic relation is observed between P0 and φ where a minimum point for P0 exist. The coordinates thus can be given by:

Φ= 6 m 2 19m+12 2(9 m 2 36m+40)       (14) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qacqqHMoGrcqGH9aqpdaWcaaGcpaqaaKqzGeWdbiaaiAdacaWGTbqcfa4damaaCaaaleqabaqcLbsapeGaaGOmaaaacqGHsislcaaIXaGaaGyoaiaad2gacqGHRaWkcaaIXaGaaGOmaaGcpaqaaKqzGeWdbiaaikdacaGGOaGaaGyoaiaad2gajuaGpaWaaWbaaSqabeaajugib8qacaaIYaaaaiabgkHiTiaaiodacaaI2aGaamyBaiabgUcaRiaaisdacaaIWaGaaiykaaaajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeymaiaabsdacaqGPaaaaa@56F4@

P o = m T s V in 2 ( m1 )( m2 ) L( 3 m 2 12m+8 )        (15) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadcfajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaamyBaiaadsfajuaGpaWaaSbaaSqaaKqzGeWdbiaadohaaSWdaeqaaKqzGeWdbiaadAfajuaGpaWaa0baaSqaaKqzGeWdbiaadMgacaWGUbaal8aabaqcLbsapeGaaGOmaaaajuaGdaqadaGcpaqaaKqzGeWdbiaad2gacqGHsislcaaIXaaakiaawIcacaGLPaaajuaGdaqadaGcpaqaaKqzGeWdbiaad2gacqGHsislcaaIYaaakiaawIcacaGLPaaaa8aabaqcLbsapeGaamitaKqbaoaabmaak8aabaqcLbsapeGaaG4maiaad2gajuaGpaWaaWbaaSqabeaajugib8qacaaIYaaaaiabgkHiTiaaigdacaaIYaGaamyBaiabgUcaRiaaiIdaaOGaayjkaiaawMcaaaaajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabgdacaqG1aGaaeykaaaa@6738@

The non-monotonicity causes instability which could be avoided if the minimum power is higher than the rated power. This could be accomplished if the value of leakage inductance satisfies the following relationship:

L< m T s V in 2 ( m1 )( m2 ) P rated ( 3 m 2 12m+8 )        (16) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadYeacqGH8aapjuaGdaWcaaGcpaqaaKqzGeWdbiaad2gacaWGubqcfa4damaaBaaaleaajugib8qacaWGZbaal8aabeaajugib8qacaWGwbqcfa4damaaDaaaleaajugib8qacaWGPbGaamOBaaWcpaqaaKqzGeWdbiaaikdaaaqcfa4aaeWaaOWdaeaajugib8qacaWGTbGaeyOeI0IaaGymaaGccaGLOaGaayzkaaqcfa4aaeWaaOWdaeaajugib8qacaWGTbGaeyOeI0IaaGOmaaGccaGLOaGaayzkaaaapaqaaKqzGeWdbiaadcfajuaGpaWaaSbaaSqaaKqzGeWdbiaadkhacaWGHbGaamiDaiaadwgacaWGKbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacaaIZaGaamyBaKqba+aadaahaaWcbeqaaKqzGeWdbiaaikdaaaGaeyOeI0IaaGymaiaaikdacaWGTbGaey4kaSIaaGioaaGccaGLOaGaayzkaaaaaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeymaiaabAdacaqGPaaaaa@6A5D@

The ZVS condition for switches at the primary side can be given by:

i L ( t o )> i L2 ( t o )       (17) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadYeaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcpeGaayjkaiaawMcaaKqzGeGaeyOpa4JaamyAaKqba+aadaWgaaWcbaqcLbsapeGaamitaiaaikdaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcpeGaayjkaiaawMcaaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeymaiaabEdacaqGPaaaaa@540E@

The relation between input inductance and leakage inductance can be given by:

L in ( 8 m 2 +8md+m2 ) L      (18) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadYeajuaGpaWaaSbaaSqaaKqzGeWdbiaadMgacaWGUbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacqGHsislcaaI4aGaamyBaKqba+aadaahaaWcbeqaaKqzGeWdbiaaikdaaaGaey4kaSIaaGioaiaad2gacaWGKbGaey4kaSIaamyBaiabgkHiTiaaikdaaOGaayjkaiaawMcaaKqzGeGaaiiOaiaadYeacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeymaiaabIdacaqGPaaaaa@529C@

The range of m, d, φ can be concluded as:

{ 0<<0.5 0<d<0.5 +d<0.5 1.1<m<1.8 }       (19) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaGadaGcpaqaaKqzGeqbaeqabqqaaaaakeaajugib8qacaaIWaGaeyipaWJaeyipaWJaaGimaiaac6cacaaI1aaak8aabaqcLbsapeGaaGimaiabgYda8iaadsgacqGH8aapcaaIWaGaaiOlaiaaiwdaaOWdaeaajugib8qacqGHRaWkcaWGKbGaeyipaWJaaGimaiaac6cacaaI1aaak8aabaqcLbsapeGaaGymaiaac6cacaaIXaGaeyipaWJaamyBaiabgYda8iaaigdacaGGUaGaaGioaaaaaOGaay5Eaiaaw2haaKqbakaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeymaiaabMdacaqGPaaaaa@5B3D@

In order to ensure ZVS, the design specification for input side inductance at the primary side is

L in  <5L     (20) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbbjxAHXgaruqtLjNCPDxzHrhALjharmWu51MyVXgaruWqVvNCPvMCG4uz3bqee0evGueE0jxyaibaieYlf9irVeeu0dXdh9vqqj=hEeeu0xXdbba9frFj0=OqFfea0dXdd9vqaq=JfrVkFHe9pgea0dXdar=Jb9hs0dXdbPYxe9vr0=vr0=vqpWqaaiaabiWacmaadaGabiaaeaGaauaaaOqaaabaaaaaaaaapeGaamita8aadaWgaaWcbaWdbiaadMgacaWGUbaapaqabaGcpeGaaiiOaiabgYda8iaaiwdacaWGmbGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeOmaiaabcdacaqGPaaaaa@446C@

The range of voltage ripple across C1 should be narrow. Thus, the clamping capacitor should be designed accordingly. The voltage across the clamping capacitor can be obtained by:

V c ( t )=( t o t ( i L1 ( t ) i L ( t ) )dt )/ C 1 + V o         (21) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshaaOGaayjkaiaawMcaaKqzGeGaeyypa0tcfa4aaeWaaOWdaeaajuaGpeWaaybCaOqabSWdaeaajugib8qacaWG0bqcfa4damaaBaaameaajugib8qacaWGVbaam8aabeaaaSqaaKqzGeWdbiaadshaa0Wdaeaajugib8qacqGHRiI8aaqcfa4aaeWaaOWdaeaajugib8qacaWGPbqcfa4damaaBaaaleaajugib8qacaWGmbGaaGymaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaaGccaGLOaGaayzkaaqcLbsacqGHsislcaWGPbqcfa4damaaBaaaleaajugib8qacaWGmbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacaWG0baakiaawIcacaGLPaaaaiaawIcacaGLPaaajugibiaadsgacaWG0baakiaawIcacaGLPaaajugibiaac+cacaWGdbqcfa4damaaBaaaleaajugib8qacaaIXaaal8aabeaajugib8qacqGHRaWkcaWGwbqcfa4damaaBaaaleaajugib8qacaWGVbaal8aabeaajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabIcacaqGYaGaaeymaiaabMcaaaa@725C@

Vc, voltage ripple across the capacitor C1 can be calculated by:

V c =max{ V c ( t xa ), V c ( t xc )  }min{ V c ( t o ), V c ( t xb )  }       (22) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiabloBjwjaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaKqzGeWdbiabg2da9iaad2gacaWGHbGaamiEaKqbaoaacmaak8aabaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4yaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaKqba+aadaWgaaWcbaqcLbsapeGaamiEaiaadggaaSWdaeqaaaGcpeGaayjkaiaawMcaaKqzGeGaaiilaiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaKqba+qadaqadaGcpaqaaKqzGeWdbiaadshajuaGpaWaaSbaaSqaaKqzGeWdbiaadIhacaWGJbaal8aabeaaaOWdbiaawIcacaGLPaaajugibiaacckaaOGaay5Eaiaaw2haaKqzGeGaeyOeI0IaamyBaiaadMgacaWGUbqcfa4aaiWaaOWdaeaajugib8qacaWGwbqcfa4damaaBaaaleaajugib8qacaWGJbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacaWG0bqcfa4damaaBaaaleaajugib8qacaWGVbaal8aabeaaaOWdbiaawIcacaGLPaaajugibiaacYcacaWGwbqcfa4damaaBaaaleaajugib8qacaWGJbaal8aabeaajuaGpeWaaeWaaOWdaeaajugib8qacaWG0bqcfa4damaaBaaaleaajugib8qacaWG4bGaaeOyaaWcpaqabaaak8qacaGLOaGaayzkaaqcLbsacaGGGcaakiaawUhacaGL9baajuaGcaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabkdacaqGYaGaaeykaaaa@829A@

The current iL1 intersects iL at three instants txa, txb, and txc as shown in Figure 5(b). The following conditions should be satisfied so as to limit ∆Vc to a smaller value.

V c V c = V c 2 V in  5%      (23) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcfaieaaaaaaaaa8qadaWcaaGcpaqaaKqzGeWdbiabloBjwjaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4yaaWcpaqabaaaaKqzGeWdbiabg2da9Kqbaoaalaaak8aabaqcLbsapeGaeS4SLyLaamOvaKqba+aadaWgaaWcbaqcLbsapeGaam4yaaWcpaqabaaakeaajugib8qacaaIYaGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaamyAaiaad6gaaSWdaeqaaaaajugib8qacaGGGcGaaGynaiaacwcacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeOmaiaabodacaqGPaaaaa@57BB@

The duty cycle of the switches at the input side is fixed to 50 with an open loop control scheme thus the value of clamping capacitor C1 can be taken as 60μF. Thus, the average voltage across the clamping capacitor can be found out by:

V c =2 V in       (24) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaadogaaSWdaeqaaKqzGeWdbiabg2da9iaaikdacaWGwbqcfa4damaaBaaaleaajugib8qacaWGPbGaamOBaaWcpaqabaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabkdacaqG0aGaaeykaaaa@47A8@

For identical input inductors L1 and L2, the input current iin can be given as

i in (t)= i L1 ( t ) i L2 ( t )      (25) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaadMgajuaGpaWaaSbaaSqaaKqzGeWdbiaadMgacaWGUbaal8aabeaajugib8qacaGGOaGaamiDaiaacMcacqGH9aqpcaWGPbqcfa4damaaBaaaleaajugib8qacaWGmbGaaGymaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaaGccaGLOaGaayzkaaqcLbsacaWGPbqcfa4damaaBaaaleaajugib8qacaWGmbGaaGOmaaWcpaqabaqcfa4dbmaabmaak8aabaqcLbsapeGaamiDaaGccaGLOaGaayzkaaqcfaOaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeikaiaabkdacaqG1aGaaeykaaaa@5659@

Thus, it is evident that if L1 and L2 are identical then there will be zero high-frequency current ripple and iin will be a constant DC current. The low-frequency ripple is also suppressed in this converter by using a dual-loop control. This increases the impedance at the output of the converter which reduces the current ripple obtained from the stacked fuel cell.

Four-phase interleaved four-switch buck-boost converter

Interleaving technology improves the converter’s dynamic response and power density making it more widely used for high-power applications [34]. This interleaved DC/DC converter is multi-phased and employs magnetic integration which reduces the converter’s cost as well as enhances the power density [35,36]. The phases interleaved strategy reduces the ripple present at the output of the converter [37]. A four-mode control strategy is proposed in [38] to improve the converter’s control strategy. For reduction in inductor current ripple, the Zero Voltage Strategy of this converter should be realised at its full range [39,40]. The schematic diagram of a Four-Phase Interleaved Four-Switch Buck-Boost Converter is shown in Figure 6. Here in Figure 6 L1---4 represents inductance & M describes the switches. The converter consists of four switches S1, S2, S3 and S4 along with an output filter capacitor Co and a shared inductor L. Here, the switches S1 and S2 form a buck bridge whereas S3 and S4 form a boost bridge both with complimentary conduction [41]. The duty cycle of switch S1 and switch S3 is denoted by d1 and d2 respectively. The converter’s voltage gain M can be achieved using the principle of volt-second balance after non-ideal parameters are ignored these parameters are parasitic components of the circuit and power loss.

M= V o V in d 1 1 d 2        (26) MathType@MTEF@5@5@+=feaaguart1ev2aaatCvAUfeBSjuyZL2yd9gzLbvyNv2CaerbuLwBLnhiov2DGi1BTfMBaeXatLxBI9gBaerbd9wDYLwzYbItLDharqqtubsr4rNCHbGeaGqiVu0Je9sqqrpepC0xbbL8F4rqqrFfpeea0xe9Lq=Jc9vqaqpepm0xbba9pwe9Q8fs0=yqaqpepae9pg0FirpepeKkFr0xfr=xfr=xb9adbaqaaeGaciGaaiaabeqaamaabaabaaGcbaqcLbsaqaaaaaaaaaWdbiaad2eacqGH9aqpjuaGdaWcaaGcpaqaaKqzGeWdbiaadAfajuaGpaWaaSbaaSqaaKqzGeWdbiaad+gaaSWdaeqaaaGcbaqcLbsapeGaamOvaKqba+aadaWgaaWcbaqcLbsapeGaamyAaiaad6gaaSWdaeqaaaaajuaGpeWaaSaaaOWdaeaajugib8qacaWGKbqcfa4damaaBaaaleaajugib8qacaaIXaaal8aabeaaaOqaaKqzGeWdbiaaigdacqGHsislcaWGKbqcfa4damaaBaaaleaajugib8qacaaIYaaal8aabeaaaaqcfa4dbiaabccacaqGGaGaaeiiaiaabccacaqGGaGaaeiiaiaabccacaqGOaGaaeOmaiaabAdacaqGPaaaaa@53E3@

It can be said that M is affected only due to d1 and d2 whereas the gain of the converter is not affected due to the phase shift angle between two bridge arms and switching frequency. The interleaving technology is provided through magnetic integration which consists of inductors. This interleaving technology is useful to reduce large ripples in input and output current, and high current stress of the switches, and improves the converter’s overall efficiency. There is a phase difference of 900 between every two phases as it drives the corresponding switch. There is no decrement in the ripples in the inductor current of each phase thus increasing the number of interleaving phases which further increases the weight and volume of the magnetic element. The significant integration of magnetic circuits to interleaved circuits improves the dynamic performance as well as reduces the losses of magnetic elements of the converter. Figure 7 shows the topology of the four switch, Four-Switch Buck-Boost Converter.

The converter here operates in a three-mode control strategy as per the input and output voltage relation where the three modes are boost, buck, and buck-boost. If the value of d1 of Buck Bridge is 1, at this instant S1 is on, S2 is off and the switching actions are performed by S3 and S4 then the converter behaves like a synchronous rectifier boost converter. If the value of d2 of Boost Bridge is 0, at this instant S4 is on, S3 is off and the switching actions are performed by S1 and S2 then the converter behaves like a synchronous rectifier Buck converter. The moment when the value of output voltage Vo is close to input voltage then all four switches will turn on at the same time and the converter will operate in buck-boost mode. At a time, two switches are turned on whereas switches forming the corresponding bridge arms are also turned on at a phase shift of 900 for preventing the direct voltage. Table 1 shows all the switching states of the converter operation. Here, Vab represents the inductor voltage.

The equivalent circuit of all operating modes of the converter is shown in Figure 7(a-d). In mode 1 shown in Figure 7(a), the load receives the stored energy released by the inductor in boost mode. This same could happen in buck mode also where energy storage by the inductor is made possible using the battery. Mode 2 occurs in boost mode as shown in Figure 7(b). To realize higher output voltage in comparison to input voltage the inductor uses more energy to charge. Mode 3 occurs in buck mode where the inductor releases stored energy as shown in Figure7(c). This mode doesn’t appear in boost mode but can appear in the Buck-Boost mode as there is a circulation of inductor current. Practically, for control purposes the time for the circulation current of the inductor should be less. The main waveforms of inductor current and voltage and driving voltage of three operating modes are shown in Figure 7(d). The waveform of the driving voltage, inductor current, and inductor voltage of the converter under three mode control for three operating modes is shown in Figure 8. There is a frequent transition of the modes in this transistor due to disturbances which could be reduced by adding ∆. The waveforms of the ripple of the inductor current and output current of each phase of a four-phase interleaved FSBB converter are shown in Figure 9. It is observed that after a phase interleaved connection there is an offset in the ripple current of the inductor.

Table 2 below shows a comparison of the Clamped H-type boost DC-DC converter, Current-Fed Hybrid Dual Active Bridge DC-DC Converter, and Four-Phase Interleaved Four-Switch Buck-Boost Converter based on parameters like Voltage Gain, switching components, diodes, etc. The table shows that each capacitor has different properties and can be used as per the functional requirement, and disturbances on load.

Conclusion

There are several isolated and non-isolated converters available in the market. The non-isolated converters are simple, efficient, and easy to maintain which makes them popular in comparison to others. This paper dealt with three such non-isolated converter configurations that are popular and have been used widely in recent times for vehicular applications. These three converters are a clamped H-type boost DC-DC converter, a current-fed hybrid DAB DC-DC converter, and a four-phase interleaved four-switch Buck-Boost converter. The performance of converters is analysed on the basis of voltage gain, size of the circuit, efficiency, and voltage stress. As seen in the study, the capacitor-clamped H-type boost DC-DC converter has several benefits wide voltage gain range while ignoring the narrow-pulse of PWM voltage waveform, lower power conduction loss of switches, lower voltage stress on capacitors and power semiconductors and lower input current ripple. Similarly, a current-fed hybrid DAB DC-DC converter has less high-frequency ripples of input current in comparison to conventional interleaving technology. The notch filter as seen here effectively reduces the low frequency. Finally, a four-phase interleaved four-switch Buck-Boost converter topology reduces ripples of output current to a large extent and improves the efficiency. This converter has three modes of operation depending on the input-output voltage relationship. They are Buck, Buck-Boost, and Boost modes. This three-mode control strategy solves the discontinuous voltage gain issue and shows good dynamic performance while maintaining a smooth transition between these three modes. Although they can be applied in various fields, they are most suitable for vehicular and power generation applications specifically for fuel cell stacks.

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